CURRENT OPPENINGS
| Job code | Job/Role/Position | Exp | Job Description | Location | |
|---|---|---|---|---|---|
| J001 | IP/SOC VERIFICATION | 3 – 10 yrs | HVLs/Tools: SV, C,ARM,OVM/UVM Domain: Networking, DDR2/3/4, Ethernet/ PCIe/Graphics |
Hyderabad, Pune and Bangalore | Apply Now |
| J002 | DFT Engineer | 3 – 12 yrs | Full chip DFT implementation & Verification of SCAN, JTAG/Boundary scan, MBIST, ATPG and Simulations | Hyderabad and Bangalore | Apply Now |
| J003 | Physical Design Engineer | 3 – 12 yrs | Physical design engineer with expertise on Partitioning, IO ring preparation, Floor planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design | Hyderabad and Bangalore | Apply Now |
| J004 | Sales Manager (International) | 6 – 12 yrs | End-to-End Sales in APAC, EMEA, UK, US & North America | Bangalore | Apply Now |
| J005 | .Net Developer | 2 – 4 yrs | Develop Application using .Net, ASP.Net,C#, WCF, MVC, SQL Server | Hyderabad | Apply Now |
| J006 | SSD STORAGE FIRMWARE DEVELOPMENT | 4 – 8 yrs | Python and embedded C Familiar with PCIe,SCSI,SAS,SATA,iSCSI | Bangalore | Apply Now |
| J007 | PYTHON AUTOMATION ENGINEER | 4 – 8 yrs | Automation framework/test scripts development in python Hands on experience on storage devices | Bangalore | Apply Now |
| J008 | STANDARD CELL LAYOUT | 3 – 8 yrs | Hands-on experience layout of digital ASICs in leading edge CMOS processes 28nm, 20nm Tools: Cadence (preferably 6.1* Open Access version), Cadence VXL, Mentor Graphics Calibre verification suite, Calibre RVE |
Bangalore | Apply Now |